1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device mask and a method for forming the same.
2. Background of the Related Art
FIG. 1A illustrates a plan view of a first background art composite mask using one mask for defining isolating regions and an active region and another mask for defining gate lines. FIG. 1B illustrates a cross-section of a semiconductor device of FIG. 1A along line I--I. FIG. 2 illustrates a plan view of a second background art composite mask using one mask for defining isolating regions and an active region and another mask for defining gate lines. Both of the background art composite masks define isolating regions and active regions to be used for isolating devices by means of shallow trench isolation.
Referring to FIG. 1A, the background art first mask defines an active region. The active region can include dense areas such as memory cells or a cell region and relatively sparse areas such as peripheral circuit regions (i.e., input/output circuits) or core regions (i.e., addressing circuits). As shown in FIG. 1A, a dense real active region is located to the left of a sparse real active region. The region other than the active region is defined as a region in which isolating regions are to be formed.
In the background art first mask, the cell region (e.g., dense) is patterned to have a narrow real active region, while the peripheral or the core region (e.g., sparse) is patterned to have a wide real active region. An isolating region in the cell region has a narrow width, while an isolating region between the cell region and the peripheral region (or core region) is defined to have a wider width. And, a gate line pattern region for forming gate lines crosses the isolating region.
A method and a structure for fabricating a device with trench isolating regions using the background art first mask will now be described with reference to FIGS. 1A-1B. First, an initial oxide film and a buffer nitride film are formed on a semiconductor substrate 1 and subjected to anisotropic etching using the background art first mask, to expose the semiconductor substrate 1 in which isolating regions are to be formed. Then, the semiconductor substrate 1 is etched to a prescribed depth to form a trench. An insulating material 2 is deposited to fill the trench isolating region, and subjected to annealing at a temperature above 1000.degree. C. to make a wet etching rate almost the same with a wet etching rate of the insulating material 2 formed by thermal oxidation.
An additional nitride or polysilicon layer can be deposited to form a layer with increased flatness relative to the insulating material 2. A photoresist film is coated on the additional layer or the insulating material 2 and subjected to selective patterning by exposure and development. The additional layer and the insulating material 2 are etched using the patterned photoresist film as a mask to open the active region and leaving the photoresist film on the isolating region. Then, the additional layer and the insulating material 2 on the active region is subjected to anisotropic etching. The insulating material 2 and the additional layer are subjected to chemical mechanical polishing (CMP) for planarizing the insulating material 2 and removing the additional layer to expose the buffer nitride film. The nitride film is removed, and ions are injected into the semiconductor substrate 1 to form a well region in the active region. An oxide film and a polysilicon layer are deposited on an entire surface and subjected to anisotropic etching using the gate line forming mask, which is defined to cross the active region and the isolating region to form a gate oxide film 3 and the gate line 4.
As shown in FIG. 1B, since the wider region in the isolating region is not completely filled with the insulating material 2, it is difficult to perform the later processes with a flat surface. Further, the insulating material 2 in the wider region of the isolating region is removed to a greater degree than the insulating material 2 in the narrow region of the isolating region by chemical mechanical polishing, which produces a dishing effect. Further, voids can be formed in the trenches.
As shown in the background art second mask of FIG. 2, a region for forming dummy active regions is defined in an isolating region between the cell region and the peripheral region (or core region) of the first mask. The dummy active pattern region further defines the mask pattern region such that isolating regions are formed at regular intervals. When the background art second mask is applied in formation of a device, the device can be formed using a method identical to the method described above for the background art first mask in FIGS. 1A-1B.
As shown in FIG. 2, a device formed thus is provided with trench regions in the semiconductor substrate 1 at fixed intervals. In the background art second mask, the trench regions can be planarized without the dishing effect because the trench regions are at fixed intervals. The gate line is formed flat crossing the real active regions of the cell region and the peripheral region. In addition, the gate line is formed flat crossing the dummy active pattern region.
However, the background art semiconductor device masks and a semiconductor devices fabricated using the same have various problems. In the case of formation of device trench regions using the background art first mask, a micro-loading effect occurs because of differences in depths and angles of the trenches resulting from differences in widths of the trenches. The chemical mechanical polishing to form device trench regions using the background art first mask causes the dishing effect in the wider isolating regions that makes a flat surface difficult to achieve for later processes. Further, step differences between trench regions of narrow width and wide width are different to overcome in planarization of the trench regions by etch back after formation of the trench regions. In addition, a problem of a parasitic capacitance forming between the gate line and the dummy active region occurs when a device is fabricated using the background art second mask.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.